1. Field of the Invention
The present invention relates to integrated circuit packaging technology, and particularly to three dimensional packages involving high density stacks of integrated circuits.
2. Description of Relates Art
There is increasing need to produce compact integrated circuit packages. Packaging technology must improve as integrated circuit clocks speeds increase because package delays contribute a significant fraction of computer cycle times. Thus, the board level computing elements (e.g., packaged dice or integrated circuit chips) must shrink, just as the size of the basic integrated circuit computing elements had to shrink to accommodate increases in chip clock rate. Also, in aerospace, aviation, and other applications, the reduction of size and weight is an extremely important goal in tis own right, independent of speed.
In the case of high speed logic or power devices, high packing densities needed to achieve these goals raise important questions of cooling. Commercial mainframe computer dissipate almost 20 watts per square centimeter, but with future generations of gallium-arsenide logic they may generate over 40 watts per square centimeter. With future ECL bipolar logic they may generate over 100 watts per square centimeter of heat.
Other problems associated with packaging advanced integrated circuit technology arise from the wire bonding, tape automated bonding (TAB), and flip-chip interconnect technology conventionally used. In particular, these technologies limit the input/output capabilities of densely packaged systems. Further, as clock speeds continue to increase, the inductance of TAB and wire bonds start to limit edge speeds and clock rates.
Hybrid water-scale packaging has been developed to address many of these problems. These hybrid wafer-scale packages consist of integrated circuits bonded to a silicon circuit board, which, in turn, may be bonded to a microchannel heat sink. Integrated circuit chips are bonded by a thin film eutectic bond to the silicon circuit board. Such bond provides intimate thermal and mechanical contact with the board. The silicon circuit board has a planarized thin film interconnect system. Laser patterning permits chip to circuit board interconnects to be fabricated directly on vertical walls of the attached chips. This laser patterning results in higher I/O density and better electrical characteristics than achievable by wire bonding or TAB. Incorporation of the microchannel heat sink reduces overall package thermal resistance per unit area by a factor of more than 50 compared to conventional computer cooling technology.
Thus, the hybrid wafer-scale packaging permits densely packed integrated circuits, while accommodating large heat flux and high pinout generally associated with fast LSI, VLSI, and ULSI parts. To achieve further advances, it is desirable to extend this technology and related technologies from two dimensions at the board level, to the third dimension at the system level.